The performance characteristics and reliability of integrated circuits has become increasingly dependent upon the structure and attributes of the vias and interconnects which are used to carry electronic signals between semiconductor devices on an integrated circuit or chip. Advances in the fabrication of integrated circuits have resulted in increases in the density and number of semiconductor devices contained on a typical chip. However, the technology of interconnect structure and formation has lagged behind these advances and is now a major contributor to limitations on signal speed in integrated circuits. The resultant need for thinner, shorter, and faster interconnects has become a major concern in the field of integrated circuit manufacture.
Integrated circuits are generally constructed from a silicon wafer which contains numerous semiconductor devices such as capacitors and transistors. Vias and interconnects allow electrical charge to be transferred from one semiconductor device to another on a single chip. Current fabrication techniques for these structures consist of preparing the surface of the silicon wafer by formation of an intermetallic dielectric layer (IDL), most commonly silicon dioxide (SiO.sub.2). This is followed by the creation of a mask of the desired interconnect structure, depositing the interconnect material (e.g., aluminum) on the IDL, and then removing the mask leaving a metal interconnect structure. Another typical method is to form the metal layer over the IDL allowing the interconnect structures to fill and then removing the excess metal through chemical mechanical polishing methods. Aluminum has been, historically, the preferred metal for use in the construction of integrated circuit interconnects.
Aluminum is widely used in the semiconductor industry because it is an inexpensive metal which is relatively easy to etch and offers good adhesion to an SiO.sub.2 IDL. However, aluminum exhibits significant electromigration effects and is generally susceptible to humidity-induced corrosion as well as to the formation of cracks or spaces between the metal layer and the IDL due to large variance in the coefficients of thermal expansion between the two materials, a process commonly known as "cold creep." Electromigration, the susceptibility of a metal to open circuit and void effects, and "cold creep" of aluminum have become more of a concern to chip designers as the desired width of metallization decreases in integrated circuits.
The problems associated with aluminum have become markedly pronounced as the geometry of integrated circuitry continues to shrink. This has led to attempts to utilize different materials to construct an interconnect system having the chemical and mechanical properties which will complement and enhance smaller and faster circuit systems. The ideal interconnect material in an integrated circuit would be an inexpensive material exhibiting the characteristics of low resistivity, minimal electromigration, possessing a similar coefficient of thermal expansion to the substrate material, and resistance to corrosion. Research has generally centered around the use of gold, silver, and copper as via and interconnect materials given their beneficial properties in one or more of these areas.
Of the various materials available, copper is perhaps the most attractive for use in integrated circuits because of its desirable chemical and mechanical properties. It is an excellent conductor with a resistivity of 1.73 micro-ohms/cm, available for low cost, and can be easily processed. Copper also exhibits far fewer electromigration effects than aluminum and therefore can carry a higher maximum current density; thus permitting faster transport of electrons. Copper's high melting point and ductility combine to produce far less "cold creep" during the semiconductor fabrication process than many other metals, including aluminum.
Although copper may be ideally suited to the fabrication of integrated circuits, it also exhibits several fabrication problems for designers. As described above, an integrated circuit is produced by initially creating a silicon wafer which contains a multitude of semiconductor devices. Next an IDL layer, generally of SiO.sub.2, is formed. In contrast to aluminum, copper is soluble in silicon and most common IDLs and exhibits a high rate of diffusion at temperatures associated with integrated circuit manufacturing. This diffusion can result in the creation of intermetallic alloys which can cause the active semiconductor devices in the silicon substrate to malfunction, rendering the integrated circuit impotent. In addition, copper exhibits poor adhesion to SiO.sub.2 which can result in the failure of electrical contacts through broken connections.
To use copper successfully in a silicon-based integrated circuit, an intermediate "diffusion" barrier layer must be placed between the IDL and the copper interconnect. Such a barrier is intended to eliminate the diffusion which would otherwise occur at the copper-IDL junction and, thus, prevent the copper from altering the electrical characteristics of the silicon-based semiconductor devices. Such a diffusion barrier is well known in the art and may be formed of a variety of transition metals, transition metal alloys, transition metal silicides, metal nitrides, and ternary amorphous alloys. The most common diffusion barriers in use are titanium nitride (TiN) and titanium-tungsten alloy due to their demonstrated ability to effectively reduce copper diffusion.
The next step is to deposit a copper layer onto the surface of the diffusion barrier. However, current methods for the deposition of copper onto the barrier layer have proven insufficient to produce adhesive copper interconnect structures with proper step coverage for today's integrated circuit applications. Prior methods that have been proposed to develop a copper interconnect layer involve numerous process steps and various treatments to obtain useable electronic signal paths. These methods have proven insufficient to address the demands of modern integrated circuit fabrication.
Deposition of metallization generally occurs through one or a combination of the following techniques: chemical vapor deposition (CVD), physical vapor deposition (PVD) (e.g., sputtering, evaporation, etc.), or electrochemical deposition. Aluminum is generally deposited through sputtering or CVD. The decreasing size of the component structure of silicon-based chips has highlighted the difficulty inherent in obtaining sufficient coverage and density from sputtering alone. CVD involves moderate to high temperatures which can lead to cold creep effects and an increased chance of impurity contamination over other methods. Therefore, electrochemical deposition offers the most precise control over the microstructure and a process which can be performed at room temperature and atmospheric pressure. This translates into the possibility for thorough coverage, less physical flaws, and a reduction in the possibility of separation due to differing coefficients of thermal expansion.
However, electrochemical deposition processes used to deposit copper directly onto a diffusion barrier have thus far been insufficient to produce an interconnect layer on an integrated circuit that exhibits reliable and high speed performance characteristics. Processes involving the direct electrochemical deposition of copper onto the barrier layer have generally resulted in films with voids and other defects. One such process, described in U.S. Pat. No. 5,151,168 (Gilton et al.), utilizes a bath in which copper ions are complexed with EDTA at a pH of 13.5. Electrochemical deposition of copper onto a barrier layer can result in insufficient cluster densities which do not allow coalescing of the clusters for film growth or produce a copper "dust" which exhibits little or no adhesion.
Further attempts to utilize electrochemical deposition of copper involve forming intermediate layers, as shown in FIG. 6. As shown, an integrated circuit can be formed using a silicon wafer 100, an intermetallic dielectric layer 102, and a diffusion barrier layer 104. To produce an adhesive surface, a copper seed layer 150 is deposited through a CVD process like that described in Edelstein, Proc. IEEE International Electron Devices Meeting (IEDM), 43, 773 (1997), which is incorporated herein by reference. After the CVD process, the integrated circuit is then placed in an electrolyte bath to undergo electrochemical deposition of a final copper layer 152 over seed layer 150. This method, however, is undesirable as it increases production costs and contamination rates by the use of multiple, non-reversible deposition steps.
Low temperature annealing has also been utilized after the deposition of copper onto a diffusion barrier layer. This method, however, increases the possibility of negative "cold creep" effects as well as a failure to provide a consistent and dense copper structure.